EDAToolsCafe, the Worlds #1 EDA Web Portal.
Search:
HP Invent
  Home | EDAVision | Companies | Downloads | Interviews | News | Discussion | Resources |  ItZnewz  | |  CaféTalk  |
  Check Mail | Free Email | Submit Material | Universities | Books & Courses | Events | Membership | Fun Stuff | Advertise |
 Browse eCatalog:  Free subscription to EDA Daily News
eCatalogAsic & ICPCBFPGADesign ServicesHardwareSIP
Email: 

News: Subscribe to CafeNews |  Company News |  News Jump |  Post News
  EDA Company News

Submit Comments Printer Friendly Version

NEC and Sequence Form Strategic Alliance to Develop Next-Generation SoC Design Closure Flow

SANTA CLARA, Calif.--(BUSINESS WIRE)--Aug. 27, 2001-- NEC Electronics Inc. and Sequence Design, Inc., the Design Closure Company, today announced a strategic alliance to develop a new ultra-deep-submicron (UDSM) system-on-chip (SoC) design flow. The flow will integrate tools and libraries to manage the complexity of UDSM designs at dimensions below 180 nanometers.

``We are pleased to align with Sequence to develop a design flow that will help achieve design closure for the highest-performance SoC designs in the marketplace,'' said Kazu Yamada, general manager of the Technology Foundation Group, NEC Electronics Inc. ``The flow will test Sequence's power management and physical optimization tools on NEC's designs for the broadband and mobile markets.''

Tools included in the development will be Sequence Design's PowerTheater suite of design planning, power reduction, power analysis and optimization products at the register transfer level (RTL). The physical design will be managed using Sequence's PhysicalStudio(TM) and ShowTime(TM) to provide design closure for signal integrity, power and timing.

``The next-generation of SoC designs requires a new approach to the issues of design planning, signal integrity, power, timing and advanced fabrication processes,'' remarked Vic Kulkarni, chief operating officer, Sequence. ``This combination of resources addresses all of these challenges through a coherent flow that delivers the highest-performing chip possible for designs with tens of millions of gates today.''

About NEC Electronics Inc.

NEC Electronics Inc., headquartered in Santa Clara, California, is one of the leading developers, manufacturers and suppliers of semiconductor products in the United States. Committed to meeting customers' cost, performance and time-to-market requirements, the company offers solutions ranging from standard products to system-on-a-chip (SoC) solutions, as well as customized products for next-generation designs. NEC Electronics also offers customers the benefits of a local manufacturing facility in Roseville, CA, and the global manufacturing capabilities of its parent company, NEC Corporation (NASDAQ: NIPNY). For more information about products offered by NEC Electronics Inc., please visit the NEC Electronics web site at http://www.necel.com.

About Design Closure

Silicon processing technology below 180 nanometers creates chips offering unprecedented performance combined with low power consumption. However, existing physical design methodologies and tools have difficulty delivering on this potential, because of complex interactions between the logic and interconnect in the chip. As designers struggle to achieve timing convergence, they invariably encounter schedule delays. The analysis-based optimization solutions offered by Sequence achieve the power and signal integrity goals set during the architectural stages of a design and thereby eliminate schedule delays.

Design closure solutions from Sequence drop seamlessly into existing design flows, protecting previous tool investment while reducing time-to-market.

Sequence Design is the first EDA company to focus comprehensively on design closure, from the architectural handoff all the way through logical and physical implementation and final verification.

About Physical Studio and Showtime

ShowTime is a static timing analyzer (STA) that includes inductance delay and IR drop for SoC and ASIC standard cell designs. It provides accurate static timing, signal integrity and power analysis of multimillion gate designs and augments existing physical design flows for fast, full chip signoff, ``what-if,'' or engineering change orders (ECO) analysis. PhysicalStudio is a design closure tool optimizing chip timing and signal integrity issues concurrently, both before and after routing. It integrates with popular standard industry routing tools, permitting existing physical design flows to reach fast, predictable design closure in silicon geometries below 180 nanometers.

About Sequence

Sequence Design, Inc., the Design Closure Company(SM), enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to tape out. Sequence's physical design software and solutions give its more than 90 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues.

Sequence has worldwide development and field service operations. The company was formed through the merger of Sente, Inc., Sapphire Design Automation, Inc. and Frequency Technology. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' Open Door(TM) partnership programs. Please visit our web site at www.sequencedesign.com.

Note to Editors: PhysicalStudio and ShowTime are trademarks of Sequence Design Inc. All other trademarks mentioned herein are the property of their respective owners. All trademarks mentioned herein are the property of their respective owners.


Contact:
     Sequence Design
     Greg Fawcett, 408/961-2365
     gfawcett@sequencedesign.com
         or
     NEC Electronics Inc.
     Michele Healey, 408/588-6620
     michele.healey@el.nec.com

Copyright 2001, Internet Business Systems, Inc.
1-888-44-WEB-44 --- marketing@ibsystems.com